A semiconductor device fabricated using a SOI (Silicon On Insulator) substrate has been widely used. An SOI substrate includes a silicon base layer, an oxide layer (BOX oxide layer) and a silicon layer formed on the oxide layer. As compared with a semiconductor device fabricated using a bulk silicon wafer, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) fabricated using an SOI wafer provides better characteristics. For example, according to a semiconductor device fabricated using an SOI wafer, there are advantages in that: a junction capacitance is remarkably low; latchup phenomenon does not occur; substrate floating effect is low; and sub-threshold characteristic is good.
In general, a SOI-MOSFET is designed so that operation current flows through a channel region located directly below a gate electrode. Now, a conventional fabrication process of a SOI-MOSFET is described using an N-channel transistor as an example referring to FIGS. 1A to 1K.
First, as shown in FIG. 1A, an SOI substrate is prepared. The SOI substrate includes a silicon substrate 101, a BOX oxide layer 102 formed on the silicon substrate 101 and an SOI layer 104 formed on the BOX oxide layer 102. Next, as shown in FIG. 1B, a device isolation region (STI) 103 is formed by a conventional process.
Next, as shown in FIG. 1C, a gate insulating layer (oxide layer) 105 is formed on the SOI layer 104 by a thermal diffusion process. Subsequently, an impurity is implanted into the SOI layer 104 by a well known technology in order to optimize the impurity concentration at a channel region in the SOI layer. After that, a poly-silicon layer is formed on the gate insulating layer 105, and the poly-silicon layer is etched to form a gate electrode 106, as shown in FIG. 1D.
Next, as shown in FIG. 1E, an impurity is ion-implanted into the SOI layer at a region (active region 104) out of the device isolating region 103 to form source/drain regions 110 of a MOSFET. The source/drain regions 110 and the active region 104 have the different (opposite) conductive types from each other. Next, as shown in FIG. 1F, an interlayer insulation layer 107 is formed over the waver entirely by a well know CVD process.
Next, apertures (contact holes) 108 are formed in the interlayer insulation layer 107 by a well know process of lithography and etching, as shown in FIG. 1G. The contact holes 108 are to be used for connecting electrically a later formed first wiring layer 109 to the source/drain regions 110 and to the gate electrode 106. Next, as shown in FIG. 1H, a metal layer (109) is formed over the wafer entirely to fill the apertures 108 by a well known sputtering process.
Subsequently, as shown in FIG. 1I, a first wiring layer 109 is shaped (formed) by a well know process of lithography and etching. After that, although an interlayer insulation layer and a wiring layer are multi-layered in general, the description of the multi-layered process is omitted.
Next, as shown in FIG. 1J, a passivation layer 120 of SiN is formed over a surface of the waver entirely by a well known CVD process to protect a surface of the device. After that, as shown in FIG. 1K, an aperture 111 is formed in the passivation layer 120 by a well known process of lithography and etching. The aperture 111 is to be used for connecting the first wiring layer 109 electrically to an external device.
According to an SOI-MOSFET fabricated by the above described conventional processes, problems are caused by: a removing (ashing) process of a resist used for a variety of etching processes and lithography process; a PID (Plasma-induced Damage) generated in a plasma process; and etc. As shown in FIG. 2, positive electric charges are trapped in the oxide layer 102 and at the boundary between the oxide layer 102 and the SOI layer 104. Such positive electric charges may include trapped charge (Qot), mobile ions (Qm), fixed charges (Qf) and interface traps (Qt). Such problems are occurred especially based on PID in an etching process to form the gate electrode; an etching process to form the contract holes; an etching process to form the wiring layer; and an etching process to form the aperture in the passivation layer.
In FIG. 2, normally only a channel region 113, which is formed by applying a voltage to the gate electrode 106, contributes current flowing when the MOSFET is operating. However, according to the conventional device, a channel 114 is also formed as a parasitic transistor around a bottom of the SOI layer 104 due to positive charges generated by PID. As a result, as shown in FIG. 3, characteristics of the MOSFET are diverged from the desired characteristics. In other words, a hump characteristic occurs.
Patent Publication 1 (JP2002-203968A) discloses a method for fabricating a MOSFET in which a LTV (Ultraviolet) light is applied during the fabrication process for a variety of purposes. It is known that harmful effect of PID, including fixed charges in the oxide layer and charged trapped between (boundary of) the oxide layer and the SOI layer, can be removed by applying a UV light to the MOSFET. However, after the process of applying a UV light, harmful effect of PID is generated again.    [Patent Publication 1] JP2002-203968A